DDR2 Controller Design Applied To SSD

As the accelerating speed of CPU operation, traditional mechanical hard disk which is reading and writing slowly have become the bottleneck of compute, which result in the development of solid state disk. We can expect that SSD will be applied largely. Flash is the storage media in most SSD. After reach certain write endurance, the reliability of flash will be rapidly reduced, and the transfer rate of flash is much smaller than the SSD external transfer rate. Introducing DDR2 as the cache of SSD, can not only solve the problem of inconsistent transfer rate, but also can extend the life of flash by merging writing operation and reducing the number of writing and erasing.According to the JEDEC DDR2 standard, we carried out the DDR2 controller functional division and implement the function of each module using hardware description language. We focused on analyzing the difficulty of the DDR2 controller--the data calibration, and used a four-step calibration to achieve the reading data transition from the DQS domain to the system clock domain. By analyzing the relationship between timing and performance of DDR2 and combining the application of SSD, we optimized the performance of the DDR2 controller, which improved the bandwidth utilization while reducing the power. The usage of pipeline technology hid the comparing and updating time of reading and writing addresses, which accelerated the processing of DDR2 controller. Built-in self test module provided two test modes that can be used to test the DDR2 chip good or bad. We built structured test platform to simulate and verify the design, which greatly shortened the DDR2 controller verification time. We used FPGA to verify the logical part of DDR2 controller and used Nanosim-VCS mixed signal simulation to verify the all-digital DLL and delay line.