The Design And Optimization Of The Saturating MAC Unit

With the highly development of the microelectronics, the feature size has been reduced below 0.18um,and the technology of the feature size 0.13um has been popular. As the feature size become smaller and smaller, the scale of the circuit integrated in a chip become more and more large , the frequency of the system also become higher and higher. In the multimedia and communication area, there are lots of data arithmetic, for example: the 3D graphic processing, DCT/iDCT, FFT, and the coder/decoder of the GSM communication system. In these area, there are lots of data arithmetic, the speed of the data arithmetic unit is very important to the performance of the system.In this dissertation, we design a 24bit x 24bit +48bit MAC unit with the ability of dealing with saturation. The saturation operation is very important in the data processing area, and the delay of the saturation MAC unit is very large. So, the performance of the saturation MAC became very importance to data arithmetic unit. In the saturation MAC unit, there are three units including multiplier, adder and the unit of dealing with saturation. In the design of the multiplier, we use the modified Booth algorithm to reduce the number of the partial product and use Wallace tree which is compose of compressor to add the partial product. By merging the MAC operation to regular multiply operation, the MAC performance is enhanced. We also use the carry look-ahead adder (CLA) as the final adder of the multiplier. In order to deal with the saturation, we add the logic to detect saturation and to modify the final value.We use SMIC 0.18 technology processing with 6 Metal layers to design the layout of the saturation MAC unit. In order to reduce the area, we optimize the floor-plan of the layout. Finally, the physical area of the saturation is 679.2um x 132.5um (0.0896mm~2). We use the nanosim+VCS co-simulation to simulate the circuit, the worst delay of the saturation MAC is 3.01ns.