Design Of Ld-celp Speech Coder Based On Fpga

LD-CELP,a low-delay speech coding technology, was promulgated by ITU-T in 1992. This technology using backward adaptations to achieve the one-way delay less than 2 ms. Its MOS scores of subjective evaluation is 4.0. The coder parameters meets the public communications network requirements. The standard is widely used in digital satellite systems, digital circuit multiplication equipment (DCME), integrated services digital network (ISDN), public switched telephone network (PSTN), voice store - and-forward systems, and other fields.The algorithm of the LD-CELP coder was studied first, and then, the hardware architecture was designed. The processing of coder was completed by an embedded DSP IP core. The input and output module processing and cache the input and output of the coder. The constant in the process stored in the constant ROM, while the intermediate variables stored in SRAM. About the software design, the operation determined by the embedded codes wrote in"assemble like"language. A specific complier translated the embedded codes to binary instructions, which ultimately stored in program ROM.The hardware and software co-simulation approved the function of the LD-CELP coder by NC-VERILOG and SIMVISION using ITU-T standard test vectors as input signals. Finally, the design was downloaded to the FPGA system, finished the function implementation on FPGA. The design only includes 20 k logic gates, 10 k ROM and 10k SRAM. The working frequency is less than 30 MHz. The FPGA chip used XILINX XC3S1000 which contains 1 million logic gates and 17280 logic units. The verification of the circuits in FPGA need some accessional circuit connected to it. The test result indicated the design fulfilled the application.