FPGA-Based Research And Design Of Turbo Coding And Decoding

In recent years,due to the rapid development of wireless communication technology,spectrum resource is short of supply.Moreover,data transmission in wireless channels is interfered by various noises.Therefore,improving the effectiveness and reliability of system transmission has become a research hotspot in recent years.As a channel code,Turbo code not only has strong anti-fading ability,high frequency band resource utilization rate,as well as strong anti-interference ability between codes,but also its performance is close to the Shannon theoretical limit value,which is highly reasearch-worthy.Because the Turbo code includes interleaving and iteration,the more iterations,the better the decoder performance.At the same time,resource consumption,decoding complexity and delay of Turbo will consequently increase,so resource consumption,decoding complexity and time delay bring up the issue that Turbo code cannot balance the validity and reliability of communication system.In order to balance the validity and reliability of communication system and reduce the complexity and delay of decoding,this paper studies Turbo coding and decoding.Specifically,the research contents are as follows:Above all,this paper analyzes the structure of Turbo encoding and decoding,interleaving,deinterleaving,scrambling and descrambling,and proposes an improved soft input and soft output Viterbi(SOVA)decoding algorithm.1.When solving the overflow problem,a method of maximizing the pre-defined storage of metrics is proposed to ensure that the accumulated metrics value does not overflow within the length of data frame,which can reduce the amount of calculation and resource consumption,and reduce the computational complexity on the basis of ensuring the algorithm performance.2.When retrospectively updating the credibility value,an improved backtracking structure is proposed.An improvement is made on the basis of the sliding window tracking structure,which only compares the decision value of the last traceback moment between the surviving path and competing path in each traceback,this improved structure can reduce unnecessary backtracking operations and reduce the decoding delay on the basis of guaranteeing the performance of the algorithm.3.This paper uses channel interleaving to modify the Turbo decoding algorithm,so that the bit error rate can be reduced when the data is transmitted in the Rayleigh channel.Secondly,this paper has performed simulation and analysis on various factors that affect the performance of Turbo codes,including different decoding algorithms(mainly MAP and SOVA algorithm),interleaver depth,iteration times and code rate,etc.According to the simulation results,it can be concluded that MAP algorithm has better decoding performance than SOVA algorithm;the longer the interleaving depth,the more iterations,the lower the coding rate,the smaller the the bit error rate,and the greater the decoding complexity.Furthermore,the analysis of the computational complexity and time complexity of different decoding algorithms shows that the improved SOVA decoding algorithm reduces the computational complexity and ensures the performance of the algorithm.Finally,according to the simulation results,the hardware design and implementation of the channel coding transmitter and receiver are carried out.Specifically,verilog language is used to write the functional modules of Turbo coding-decoding,interleaved-uninterleaved,and disturbing-undisturbing.Besides,simulation verification is carried out on the functional modules using simulation tool.The comparision results between simulation and theoretical results show that the hardware design of each functional module meets the requirements.In the end,the paper uses the Zynq 7000 development board as the system verification platform,downloading the program of transmitting system and receiving system respectively,useing the online analysis tool ILA to obtain the coding and decoding waveform and analyze it.The results show that the system works normally in FPGA.