Study On Ic Test Parallelism Improvement And Test Program Optimization

Semiconductor test is indispensable process in the semiconductor industry, it run through all processes from IC design to production roll in. Because test cost take more and more proportion in whole cost, in order to save cost, we put forward test parallelism concept. So test many devices at one time. This thesis introduce how to complete test parallelism improve project.At first, briefly state automatic test equipment principle per Teradyne J750 tester. Analyze test theory and method about some modules of SOC (System on chip). Should upgrade test system in order to complete test parallelism improvement.After that, this thesis introduces the parallelism methods, including software and hardware improvement. We researched and improved new match method in order to test many devices at one time by Teradyne help. It recommends test pattern, and how to archive test match purpose using VBT code. Complete test program improvement after two methods mutual cooperation. Make tester test device improve from one to eight once a time. This is the important and difficult points in this project improvement.In the next place, redesign new load board. Introduce load board design detail and attentions which impact on test robust performance. For example: how to forbid hot switch, how to select relay, load board layout and wire arrange principle, and so on.Finally, this thesis introduces how to optimize test program, ECID (Electrical Identity) application and advantage at test process, and the methods to analyze test issues and matters by using statistical and six sigma methods, and so on.Efficiency is enhanced and the costs are saved by parallelism improvement;hardware can be used for a longer time and test stability is increased by load board re-design;1st pass yield has been raised and the rest rate has been reduced by optimizing test program. To sum up, produce efficiency is enhanced, cost reduction is strikingly by these improvements and eventually optimization of the semiconductor test has been achieved.