Research On Hierarchical Partition And Multi-objective Mapping Technology Of Noc

In recent years, a new integrated circuit architecture called Network-on-Chip (NoC) becomes the hot issue of SoC research. It transplants the technology of the computer network into the chips design. The NoC has a better scalability than the bus architecture and is more applicable to large-scale SoC design. However, it takes more area resources and power than the bus architecture. The NoC design method links the parts of IP core with bus architecture to form a local subsystem, which connects with NoC communication nodes through network interface. Thus, the NoC could make full use of chip resources better.As a part of the fundamental technique research task, "High Performance Computer and key software", which is a project of the National High-Tech Research and Development Program of China (863 Program), the dissertation studies the two problems:hierarchical partition and mapping technique, which are key techniques of the NoC design. The destination of our NoC design is to optimize the communication architecture, the communication energy and delay. The main work and achievements are as follows:1. This dissertation analyzes the NoC architecture and design method. And based on systemic, we summarize the hierarchical NoC design scheme. It sums up the relative components and routing technology of the hierarchical NoC platform. Moreover, the relative routing technology of NoC, such as XY routing algorithm, is introduced. But when the link failures are in regular of networks on chip, XY routing could not keeps the communication natural. To solve this problem, a new adaptive routing algorithm based on the awareness of link-state is presented. This algorithm can keep the communication well after the link failures.2. In hierarchical NoC design, aiming at the communication localization and making full use of resource node area, an IP core Clustering algorithm is proposed. The algorithm is constructed with the rules of "dependence first", "earliest time first" and "fragment reuse". On the condition of combining the IP cores firstly, which have a main communication of the system, this algorithm makes full use of the resource node area of the NoC. Comparing with the k-Clustering Algorithm and with an experiment of certain application, it is shown that utilizing the clustering algorithm, we may allocate on-chip communication efficiently, improve system performance, make full use of space resources and decrease hardware cost.3. Conventional multi-objective programming which aggregates the energy and delay by forming a linear combination of them, can not make good tradeoffs between the key target of energy and delay. A multi-objective mapping algorithm based on NSGA-Ⅱis proposed in this dissertation. First of all, the communication energy and delay model is constructed. Then, it is pointed out that delay can be optimized indirectly by means of optimizing distribution of link load. At last, an energy-and delay-aware mapping algorithm of NoC based on the model is proposed. In order to have the low energy and low delay system, the mapping algorithm makes use of the fast nondominated sorting approach, adopts elitist strategy and a crowded-comparison approach of NSGA-Ⅱ. Experimental results show that this mapping approach makes the good tradeoffs between communication energy and delay, and achieves prominent low energy and delay effect.