Research On High-performance Mapping Algorithm For Network-on-Chip

With the development of super-large-scale integrated circuit technology,more and more processing cores can be integrated on a single chip,and consequently,the amount of inter-core communication is increasing.As the infrastructure of inter-core communication in multi-processor system,the network-on-chip effectively solve the complex problems of the communication between multicores.The research on No C has attracted widespread attention in recent years.As one of the main problems in network-on-chip design,mapping optimization has proved to be an NP-hard problem.Therefore,it has become a challenging problem to efficiently allocate the application core to the appropriate nodes of the network with the aim of optimizing the performance of the system under certain constraints.In this thesis,the research background and significance of the No C was first described.In addition,we summarized the key technologies and the development status of current No C research.Then,starting from the problem of mapping optimization,the impact of different mapping strategies on system performance was analyzed.Finally,research achievements of existing mapping optimization algorithms were reviewed from the point of view of topology size.The major research and findings are shown below:Aiming at addressing the problem of competition caused by the sharing of TSV(Through Silicon Vias)vertical link in the cluster-based three-dimensional No C and the problem of uneven temperature distribution caused by the vertical stacking of the chip,a mapping model with network competition and temperature equalization as the optimization goal was built.In this model,we measured the degree of competition in the cluster No C based on the N:1 shared TSV by the competition factor and quantified the temperature difference between the layers due to the difference from the heat sink position.A memetic algorithm was designed to solve the model.In this algorithm,the local search operator was introduced into the global search operation,which enhanced the ability of the individual to search the feasible solution in the population.The simulation results showed that compared with the existing algorithms,the proposed algorithm can lead to mapping results with better performance in competition and temperature distribution.Considering the influence of the processor unit faults on the implementation application and system performance,we proposed a low-power mapping scheme based on fault perception and resource sharing.Based on the communication relationship between the application cores,the scheme defined the key factors based on the Page Rank sorting idea and added the virtual application core with the backup function according to its level,and meanwhile,a shared mechanism for the application cores with the same functional type was utilized to reduce the backup cost.In addition,considering the influence of the location relationship between the virtual core and application core on the energy consumption before and after the failure of the system,we constructed the mathematical model with the objective of energy efficiency,and it could be solved by designing an improved ant colony algorithm.The algorithm improved the pheromone update in the traditional ant colony algorithm,improved the convergence speed and avoided the occurrence of stagnation.Simulation results showed that the scheme proposed in this paper had lower network area overhead,and the improved ant algorithm could achieve lower energy consumption than the existing mapping algorithms.