Research On Collaborative Optimization Of Network On Chip Task Mapping And Online Testing

With the rapid development of integrated circuit technology,the networked interconnection structure based on on-chip network has been widely used in various system-level chips due to its own unique advantages as the mainstream solution for inter-core communication in system-level chips.At the same time,the intermittent failure rate of the on-chip network will continue to increase as the level of chip integration continues to increase.How to detect intermittent faults in the on-chip network online to improve the reliability of the on-chip network and the entire system has become an important issue.Based on this,this paper utilizes the scheduling and provisioning of resources in the task mapping process of the system to achieve the collaborative optimization of on-chip network task mapping and on-line testing.The main work is as follows:(1)According to the characteristics of intermittent faults and application mapping process,the idle paths and the components coupled with the idle paths are embedded in the test process during application task mapping.Breaking the traditional router-centric test architecture,a new path-based test architecture is presented.In this way we can guarantee the reliability of the on-chip network without affecting the operation of the system.(2)This paper studied the discontinuous task mapping algorithm,aiming at achieving the dual optimization of system performance and on-line testing.In the collaborative optimization scheme of task mapping and on-line testing,the priorities of fault detection and task mapping are clarified,which also established the metric parameter of online testing and mapping algorithm.The first node mapping algorithm is proposed to complete the first task selection and avoid resource fragmentation according to consider the path test information.Secondly,the test-aware mapping algorithm centering on the first node is present,which completes the task ranking based on the distribution of traffic weights,and considers the test results and test traffic flow to avoid the use of untested paths.(3)This paper established and improved the processing unit state machine execution model and application management module of the on-chip system simulation platform EsyMap,and built an on-chip multi-core system simulation platform consisting of the on-chip system simulator EsyMap and the on-chip network simulator ESY-Net to simulate,which completed the analysis and evaluation of system performance and system reliability.The simulation results show that the mapping algorithm has obvious advantages in terms on-line test under different system utilization.The maximum test time is reduced by 43.8%,the average test time can be reduced by 38.1%,and the test interruption rate is also reduced largely.At the same time,when introducing the online test to consider the path test information,the system performance does not significantly decrease,and there is a significant improvement when compared with the FF?NN and CoNA algorithm.