Research On Architecture And Mapping Techniques Of Network On Chip For Real-time Complex Systems

With the fast development of semiconductor integrated circuits (ICs), future Systemon Chips (SoCs) will integrate hundreds even thousands of Intellectual Property (IP)cores to implement ever-growing functionalities. In this trend, SoCs will face thechallenges of design, verification and manufacture. As a result, the traditionalbus-based communication structure becomes the bottleneck of SoC development inprocessing speed, power, area, throughput and reliability. To solve these problems,Network on Chip (NoC), the communication-orented integrated circuit, is proposed asa new interconnection structure.The development of wireless communication technology brings great changes to thehuman society. Since Software Defined Radio (SDR) technology can easily revisefunctions by software updating, and possesses great flexibility and scalability, it'swidely used in the wireless communication systems. Signal processing in SDR isfeatured by real-time and data-driven, which is different from traditional scientificcomputation. As the technology develops, the traditional platforms based on singlecore or simple multi-core cannot meet the high complexity and computation thedemands of practical communication systems.In future IC designs, large scale parallel processing will replace the traditional serialprocessing to improve the processing ability and speed. Since NoC is featured by hightransmission efficiency, low power consumption, great scalability and reliability, thelarge scale multi-core parallel processing platform, providing both strong processingability and high computation speed, with power and area advantage, becomes theimplementation foundation of the future communication systems. The state-of-the-artNoCs are based on general-purpose systems and lack the support to the real-timecomplex systems. According to this background, this dissertation studies architectureand mapping techniques of NoC under the consideration of real-time, concurrent,pipelining and etc. It also establishes design methodology foundations for risingtechnologies, such as3D ICs and on-chip wireless interconnections. In chapter2, the dissertation proposes a self-similar NoC traffic model based onmultiple parameters to provide accurate benchmarks for NoC designs and verifications.Using theoretical derivation and experimental method, this chapter establishes anMPSoC information relevence model, and provides an empirical fitting functionbetween the parameters of the relevence model and Hurst parameter, and establishs themethod to estimate Hurst parameter of NoC traffic. The case studies prove that thistraffic model can achieve an approximate and effective Hurst parameter.In chapter3, the dissertation proposes three high-performance3D NoC architectures.De Bruijn graph is used as the topology in physical horizontal planes by leveraging itsadvantage of small latency, simple routing, low power, and great scalability. Enhancedpillar structures, rings, and virtual planes are used for the vertical interconnection. Thedissertation designs two shifting based routing algorithms to meet separateperformance requirements in latency and computing complexity and fault-tolerantrouting to guarantee reliable data transmission. The simulation results show that theproposed3D NoC architectures can achieve distinct performance enhancements.In chapter4, the disseratation studies the multi-objective mapping algorithm forreal-time complex system on NoC platforms. It adopts optimized energy model andspecialized constraints for DSP systems, such as injection rate, iteration bound, etc, tooptimize the energy and the I/O critical delay simultaneously. Meanwhile, it uses fineparticle task division and a multiple-to-multiple mapping model to increase theprocessing efficiency and pipeline concurrency. The case study proves that theproposed mapping algorithm achieves lower power consumption and I/O critical delaythan traditional genetic mapping and random mapping.In chapter5, the dissertation proposes a dynamic wireless NoC architecture based onirregular topologies. It exploits the flexibility and broadcasting feature of the wirelesschannel to design a dynamic bandwidth allocation scheme, simple multicast routingand special virtual channel control logic. It also provides a topology and mappingco-design, which optimizes topology and mapping simultaneously with the specificconstraints and objectives. The case studies prove that the co-design method canachieve remarkable performance enhancement compared with the traditional mapping.