An Fpga Based Design And Implementation Of Evolvable Cpu

along with the rapid development of railway and popularization of passenger dedicate line, there is higher and higher requirement of train control system. It is an important assignment of keeping driving safety and improving operating efficiency.In the train control system, the I/O interface is responsibility of physical level data transmission between equipments, once faulty happen disastrous consequences will be made. The I/O interface module based on structure of distributed safety computer is realized on soft core system on a chip. The method can not only improve the safety of the system, reduce reaction time, but also extend safety computer module and realize the interface generalization.The paper leads into the concept of evolvable hardware (EHW) and introduces the content and development of EHW, and point out the advantages and disadvantages of EHW in fault-tolerant systems. To guarantee the security of the train control system and the demand of I/O interface between equipments, we propose a new method of designing I/O module which is based on the structure of distributed safety computer. The method realizes I/O function by MIPS CPU soft core system on a FPGA, and guarantees the reliability and service performance of the system by improved evolvable hardware scheme.The paper gives a result of reliability parameters, and the new CPU design based on evolvable hardware is introduced in detail. At the end of this paper, we emulate the modules of safety I/O, and give the emulation results.