Research On Digital Evolvable Hardware And Fault Tolerant Techniques

With the rapid development of information technology, modern electronic system has been demanded to adapt to task and environment. Future trends in modern electronic system design include complex function integration and multi-scenarios application integration. In order to build an adaptive, self-healing electronic system, inspired from the evolution of nature, a brand-new research domain called evolvable hardware(EHW) has been established. This thesis focuses on the techniques for the digital evolvable hardware, with respect to evolutionary algorithms, evolutionary fault tolerant techniques, design techniques for evolvable platform and evolutionary fault tolerant system.Evolutionary algorithm(EA) is the theoretical basis of evolvable hardware, as well as the primary tool for combinatorial optimization and global search. An elitism based compact genetic algorithm(CGA) with adaptive mutation rate(ECGAAMR) is proposed. To maintain good convergence, the elitism strategy is employed to ensure that the best candidate remains in the next generation. Furthermore, an adaptive mutation operator is proposed, which can enhance the local exploration efficiency of ECGAAMR. A configurable and parameterized hardware structure is proposed, due to the limitations of traditional hardware implementations methods.Online evolutionary self-repair is an important application field of EH. Current evolutionary repair methods suffer from low convergence speed, a relevance ranking based fault location method is proposed to address this problem. The proposed method utilizes fault location information to constrain the search space of EA, which improves the speed of evolutionary repair effectively. Experiment was conducted to verify the effectiveness of the proposed method. The experimental results show that our method achieves higher convergence speed. The test configurations of our method could be generated during design phase, which relieves the computational overhead of the online fault tolerant system. Furthermore, the performace of our proposed method is independent of the circuit structure.An efficient and flexible evolvable platform plays an important role in the research domain of intrinsic EHW. In this paper, we propose a lookup table(LUT) manipulation based dynamic partial reconfiguration(DPR) method, where no detailed information of bitstream is needed. A bitstream relocation based DPR method is proposed for the large scale evolution applications. The configuration memory overhead for reconfigurable module can be saved by using bitstream relocation technology. In addition, the bitstream compression method is also employed, which not only reduces the memory overhead but also brings high reconfiguration speed.Due to the high logic resource overhead of traditional triple modular redundancy(TMR), the dynamic redundancy method is employed. A multi-layer repairing mechanism could be implemented by combining dynamic reduncancy and evolutionary refurbishment. A dynamic redundancy based evolutionary self-repair system is designed based on the results of this study. The system can be switched among simplex, duplex or TMR mode by DPR. As a result, the balance between logical resource overhead and system reliability can be achieved. In addition, in order to verify the fault tolerant capability of evolutionary repair method, we propose a DPR based fault injection method based on the analysis of the single event effect and permanent aging failure mode. Experimental and fault-tolerant performance evaluation results show that the system has high reliability and real time characteristics.