Research Fault Tolerance Methods Based On Evolvable Hardware

Evolvable Hardware (EHW) refers to hardware that can change its architecture and behavior dynamically and autonomously by interacting with its environment. The prime motivation of EHW is to simulate the nature of evolution on a reconfigurable hardware platform. With self-adaptive, self-organizing and self-repairing feature, EHW has opened up a new way for hardware fault-tolerant. The Hardware designed by EHW method not only can realize the self-test and self-repairing when there is a fault in the hardware, but also can find some unknown fault. There are great value of practicality and theoretical meaning to research fault-tolerance based on EHW in the high reliability design field, especially in the nuclear industry, space aircraft, deep-sea exploration and military.The purpose of this dissertation is to research the fault-tolerance method based on EHW. The research includes rapid convergence algorithm for circuit evolution design, constructive method for heterogeneous hardware redundant system and the optimization design in embryonics applications. The main research works of this dissertation can be summarized as follows:(1) Against to the problem of slow convergence speed and poor scalability in the circuit evolution design, the dissertation has studied the structure character of complex logic in the circuit and found that it needs many layers connect and proposed a novel mutation operator introduced into Evolution Strategy (ES). The novel mutation is Short-Link-Priority (SLP) mutation, which not only accord with the structure character of relatively complex logic circuit, but also can greatly reduce the search space of evolution algorithm and accelerate the convergence the evolution. On this basis, this dissertation has combined the SLP-Mutation ES with current decomposition method, which is a circuit evolution design method for solving the scalability problem. The PSL_Mutation ES makes up for the decomposition method deficiency of using too many gates and lack of creativity. The experiments results demonstrate the validity of the proposed method.(2) A constructive method for evolutionary redundant system was proposed. This method can solve the problem that the reliability of redundant system will decline when the correlation fault occurs. This dissertation researched correlation fault in two aspects and proposed the corresponding methods. First, we proved that the reliability of heterogeneous circuit redundant system is higher than isomorphic system considering the correlation failure, and proposed a method to construct the redundant system using heterogeneous circuits and Favorable vote principle. Second, we defined the fault correlation coefficient to measure the degree of being fault at the same time between two circuits, and then deduced the reliability fomula using fault correlation coefficient. The analyses show that the number of redundant circuits is not the more the better, it is necessary for a high reliability redundant system not only to use heterogeneous circuits but also to consider optimal selections of both the redundant circuits and the redundant number We proposed a constructive method for heterogeneous hardware circuits redundant system based on genetic algorithm, which can rapidly construct the system with high reliability.(3) Design rules of high reliability embryonics in pratical applications were proposed. Embryonics system is a self-repair and fault-tolerant system based on the mechanism of multi-core embryo development. It has the characteristics of self-grow, self-detection, self-repair and simple reconfigurable mechanism, and has become the research focus of Evolvable Hardware in the recent years. The typical embryonic system is a cell array, which realizes fault-tolerance by cell redundancy and reconfiguration. Firstly, a question was proposed that the same embryonic array with different active node arrays would result in different reliabilities when the total number of active nodes was fixed Secondarily, aiming at the n*n embryonic array system, we analyzed the optimal design rules for the active node arrays theoretically and experimentally respectively based on row elimination and cell elimination fault-recovery strategies.