Modified Algorithm Of Hard Decision Decoding And Fpga Realization For Tpc

The channel coding is an important component in optical fiber communication systems. As a new type error correcting code of forward error correction (FEC) technology, Turbo product codes (TPC) has good capability of error correction which is close to the Shannon limit.And TPC has become a hot topic in the channel coding area.Up to now, most researches for TPC are mostly based on soft input and soft output (SISO) decoding. But comparing with SISO decoding, hard input and hard output (HIHO) decoding has the advantages of low complexity, simple structure, easy realization and rapid decoding speed.The thesis takes Extended Hamming codes as component codes of TPC. In order to avoid the problem of unsatisfactory decoding performance of conventional TPC hard decision decoding algorithm, two modified schemes based on conventional CHDD algorithm are proposed.To the issue of a high bit error rate (BER), a modified hard decision decoding algorithm is proposed according to the feature that some error symbols can be detected without being corrected by CHDD. The algorithm based on multiple iteration steps of CHDD algorithm can correct the wrong symbols by detecting them, estimating the total number, constructing the candidate sequences and then selecting the optimum sequence among the candidates. The simulation results indicate that with a BER of 10-5 the modified algorithm can enhance a 0.9dB gain comparing with the conventional algorithm, while decoding complexity is relatively increased.To the issue of a high wrong frame rate with a low signal to noise ratio (SNR) of the CHDD algorithm, another modified algorithm is proposed according to the point that during the CHDD decoding the column-row and the row-column is possible different. The simulation results indicate that with a 1dB-4dB SNR the modified algorithm can reduce 30% wrong frames comparing with the conventional algorithm, while the performance is better than TPC decoder chip of AHA.Finally, the total design based on FPGA of encoder and decoder is accomplished. And the decoder has been realized by the second modified algorithm. The system mainly designs encoder, decoder, selector, serial-to-parallel module and synchronization module. The simulation shows that the TPC decoder can complete within 440us under a 1 MHz clock.