Research On Decoding Algorithm For TPC And FPGA Implementation

Channel coding is used usually used to improve system performance in communication system.In communication systems,Channel coding which has been widely used in practice is usually used to improve system performance in communication systems.Now there are high performance coding chip products which are widely used in communications,information storage and so on.However,due to technical blockade,the domestic high-performance Turbo codec chip is not available.The codec chip requires the driving of the master chip in the project,and allocates the corresponding routing space and I/O resources for it.Therefore,based on a reasonable algorithm,the coding system implemented by FPGA can save resources,achieve high-speed parallel processing,and have good portability.In this paper,the basic theory of Turbo product code is studied,and the traditional theory is analyzed.The influence of decoding parameters on the decoding output is studied.The existing decoding algorithm is adjusted from the point of view of logical design to design a coding system with high decoding speed,stable performance and small resource occupation.The main decoding algorithms of Turbo product codes are studied as follows:The hard decision decoding algorithm can be applied to special bit transmission system,and has good performance and high signal-to-noise ratio conditions.The structure is simple,the decoding time is small,and the resource occupation is low in the FPGA engineering implementation.On the basis of retaining the advantages above,error correction and iterative methods are adopted to improve bit error rate performance.In this paper,Matlab simulation is used to verify the performance of the algorithm,and the FPGA logic sequence diagram is used to further implement the algorithm and verify the results.On the basis of the good BER performance of soft decision,the parameters that affect the decoding speed and performance in the decoding process are studied.And simulation verification is carried out by Matlab.If the BER performance is not affected as much as possible,the mathematical calculation,decoding structure,decoding parameters and decoding process are adjusted respectively.Finally,through the FPGA logic optimization,high throughput,low resource utilization,good portability of the coding and decoding system design.