Research On Extended Shortened CRC Code And An FPGA Implementation Of CRC-RS And CRC-Turbo

The paper items from a project on developing communication devices. The implementation of CRC-RS decoder in the project asks for an adoption of RS and extended shortened CRC codes.Although extended shortened CRC codes have been used e xtensively i n c ommunication sy stems, t he r elative d ocuments o n t he c odes a re little.Thus, on the basis of the common CRC codes, the paper brings forward a concept of extended shortened CRC codes. Extended shortened CRC codes and nonlinear extended shortened codes are studied in the paper. Through a performance analysis and simulation on generated methods, maximum minimum distance, undetected error probabilities, code weight distribution, good extended shortened codes are determined and general rule is concluded.Furtherly, the paper generates nonlinear extended shortened codes. After a study of many kinds of methods to generate nonlinear extended shortened codes, four kinds of nonlinear extended shortened codes are generated. Also the four kinds of methods are analyzed and simulated. The theory of extended shortened codes is a complement of the theory of the common CRC codes. A new selective standard is presented for GSM system.In hardware implementation of CRC-RS, a comparison between the two fast CRC calculations is given and a measure to solve the difficulty in control of data stream between CRC module and RS module is given. In hardware implementation of CRC-Turbo, many commonly used Turbo decoders are introduced. On a comprehensive consideration of the coding-rate and complexity of hardware implementation of Turbo decoder, a high coding-rate parallel Turbo decode algorithm is designed and a controller structure applicable to different decoding algorithms is presented.