The Design And Implementation Of Floating-point Multiplier For YHFT-DX

Multiplier, the core of real-time high-speed signal processing system, is the key component in high-performance DSP. With the extensive application of DSP chip, digital multiplier is becoming the key part of DSP, and its design is being paid more and more attention.This paper discusses the floating-point multiplier's design and implementation of YHFT-DX. As a high performance fixed/floating-point DSP, YHFT-DX demands high performance of its floating-point multiplier in order to meet the requirements of high-speed floating-point operations. YHFT-DX floating-point multiplier provides the functions including single-precision floating point multiplication, double precision floating point multiplication, single/double precision floating point multiplication and 32-bit fixed-point multiplication.This paper discusses the IEEE-754 floating point standard that YHFT-DX supports, and analyzes the standard about floating point format, accuracy, range, rounding, and normalization. We make an in-depth research on algorithm and structure of multiplier that are the two key factors determining the performance of a multiplier.For algorithm, it is to analyze the number, speed of the partial product and complex circuit of the partial product. Generally speaking, the fewer partial product, the more complex and slower the partial product circuit is, so both need considering to select the best algorithm. Analysis of the structures is to study the sum-speed of partial product and structure regularity.Finally, we adopt Booth 2 encoding algorithm widely used now and at algorithm and 4:2 Compression Tree Structure which can better achieve the sum-speed of partial product and structure regularity.4:2 Compression Tree Structure adopts the idea of carry save and its result is expressed with the pseudo sum and the carry. In order to get the exact result, we need to add the pseudo sum with the carry, so this paper also designs a high-speed carry propagation adder.The floating-point multiplier in this paper adopts a 4-stage pipeline structure under 0.13um CMOS technology of a third-party company. The synthesize result shows that, the floating-point multiplier can work at the frequency of 500MHZ. Its performance meets the requirements of YHFT-DX. The area is 67529.36um2. The power is consumption 22.3424mW.