Study And Design Of Floating-point 32 Bit Parallel Multiplier

With the development of the VLSI technology, multiplier which used to be finished by software becomes a very important component in data-path of CUP and DSP. This paper's work is the research of float-point multiplier. At first we introduce the data-format of IEEE-754,including formats, kinds and transformations between single precision to expanded precision. Then we do research and discussion on some important steps, including algorithms, methods of creating partial products and adders, after comparing many methods we choose 2-steps booth algorithm, inverse polarity CSA adder partial product array and Wallace-tree structure ,CSKA-CLA adder. The design of 32bits float-point multiplier including : mantissa multiplier, exponent adder, normalization etc .At last we give the result of design and verification .Specially we design a IP for this multiplier.