The Design And Implementation Of 600MHz Bsu Of YHFT-DX

The design of YHFT-DX DSP's Branch&Shifting Arithmetic Logic Unit lead to deeply research on DSP CPU core's execution unit design and accomplish the 600MHz performance goal of BSU.Several main tasks are showed below:1) Analyzing instruction sets and arithmetic of BSU,introducing the pipeline flow for BSU.Partitioning for exploit high speed and more parallel execution for implementation while simplifying complex situation.To dividing modules,we take the approach of decode against execute stage and full-custom against semi-custom, top design is divided into 2 big submodules while execution stage is divided into 7 blocks. According to synthesis design result,using semi-custom method to implement decode module and full-custom method to implement executing module,researching on mixed method design flow.2) Using full-custom design to complete critical path design of BSU. Design critical module of BSU that have influence on performance by full-custom circuit and layout method. Register that have big driving ability is used to store control signal related with operands select section, for cutting logic stage in operands select path as well as enhance performance of full-custom module. Deeply researches are made to implement saturation judging module. A comparison among three approaches of results selecting lead to use a techniques that effectively resist"1-1"signal overlap which has low power and high speed performance. Two stages shifting and asymmetry leveling approach is taken to implement 40 bit left and right shifters, and 32-bit all-bit-of-1 right shifter is used to implement bit clearing and setting operations.3) Accomplished logic synthesis and physical design of BSU. Build logic synthesis design environment, research the design constraints and timing closure techniques, and focused on command latch modules and the overall of the top design logic synthesis. Physical design aiming at detailed integration of BSU, and mainly addressed structure of latch module, designed power network and clock tree. Fully analyzing the integration of the whole design and automated extraction of Liberty file and LEF file.4) Accomplishing functional and timing verification of BSU. Analyzing RTL design verification and circuit functional verification design flow. Finishing RTL level verification platform setup, stimulus extraction and loading design flow. Functional verification of full-custom design of BSU is implemented by dynamic simulation and formal verification methods. The critical timing is examined by STA approach ,the Reg-to-Reg max delay is 1.6ns, meeting the timing requirement and achieve the 600MHz design goal, the average power consumption of design is 30mW.