Research Of Reducing Power Consumption For NoC Test

With the development of IC (Integrated Circuit) manufacturing technology, not only the scale of IC but also the clock-frequency is increasing rapidly. More and more full-featured and complex IP cores can be integrated in a single chip. SoC (System-on-Chip) which adopts bus architecture can not meet the needs of the IC technology in the near future. Therefore, some scientists proposed the concept of NoC (Networks-on-Chip), which has good scalability and parallel communications capability, can meet the needs of the new design of IC. NoC uses a large-scale multiplexing technology which can greatly improve the productive efficiency, and reduce development cycle of a chip, and accelerate to market. Testing of IC has become a critical part of the implementation processes in NoC. The proposal of NoC is to be applied to larger scale integrated circuits; test power consumption will become large. So the control of testing power is becoming more and more important. Excessive test power often leads to partial or the entire network damaged. This thesis focuses on some testing methods in NoC, and proposes a low power test method aiming at the communication architecture and router's fixed-port for 2D Mesh structure.The main works in this thesis are as follows:[1] This thesis introduces development of SoC, and current problem; and describes the proposal of NoC, development and researches of NoC, including the basic composition and topology of NoC's communication architecture. Following, the thesis depict dynamic researches on NoC test, the significance of low-power test and development of low-power test focusing on 2D mesh.[2] A test method for the communication structure of NoC is presented. In the 2D Mesh structure test, the number of packets transmitted is proportional to the test power consumption. The method analyzes the features of 2D Mesh, and divides it logically. Then, it make the router at different locations adopt the corresponding data forwarding approach to reduce the generation of data packets. Experimental data show that the method can effectively reduce the power of the communication architecture, and the test time has been effectively reduced.[3] A low-power testing method is presented, which is based on the stuck-at port fault model in the 2D Mesh. This method focuses on reducing the testing power consumption by reducing the repeated test packet, and it specializes for the stuck-at port fault of router in the 2D Mesh network. This method can effectively detect various types of fixed-port faults, while the total test power is also greatly reduced.