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Design Of FPGA Prototype For HE-AAC Audio Decoder

Posted on:2011-01-23Degree:MasterType:Thesis
Country:ChinaCandidate:J Q HuangFull Text:PDF
GTID:2178360308973168Subject:Electrical theory and new technology
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High efficiency advanced audio coding (HE-AAC) for MPEG-4 is one of the state-of-the-art audio coding standard, which can deliver better audio quality, higher compression rates, more channels and varieties of sampling rates. And it has been adopted by the standardized Digital Radio Mondiale (DRM) system and the 3rd Generation Partnership Project (3GPP). This paper focuses on the optimization of MPEG-4 HE-AAC decoder from algorithm to system architecture, from circuit design to FPGA prototype emulation.The main contribution of this thesis is as follows:(1) Optimizing the MPEG-4 HE-AAC decoding algorithms. The 2048-point IMDCT altgorithm has been transformed into 256-point IFFT or 64-point IFFT, and the 1024-point QMF has been transformed into 64-point DCT-IV, which reduces the multiply cyes by 8.59% and adder cycles by 10.41%.(2) Optimizing the system architecture. A Global-serial Local-pipeline technology is used to optimizae both area and speed of the HE-AAC decoder. The trade-offs between the speed and area have been studied. Pipeline circuits are only designed between the noiseless decoder and inverse quantifier, as well as between temporal noise shaping (TNS) and Filterbank modules. Through this technique, optimized decoding speed has beeb achieved with less resource consumption.Otherwise,three control methods are used to implement the architecture.(3) Optimizing HE-AAC hardware circuit and prototype. Hardware-parallel implement method is used in the Huffman decoder, by which the Huffman tables are implemented by combinational logic. Because Huffman coding is a ex-coding method, so the First-zero logic can be used to reduce the resource cost. IMDCT module is implemented by IFFT, while AQMF and SQMF modules are implemented by sharing DCT-IV module, with recourse cost savings of the ALUT 29.4%, the memeroy 33.3%, and the register 27.8%. In bitstream analyzer module, two barrel shifters are used to in ping-pang accessing model, which has greatly reduced the memory accessing time.
Keywords/Search Tags:HE-AAC audio decoder, FPGA design, systematic design, RTL design
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