Design And Implementation Of Systematic Polar Code Encoder And Decoder Based On FPGA

In 2008,Arikan proposed the Polar code based on the channel polarization and proved that Polar code can approach of the channel capacity with infinite code-length.In this thesis,the encoding and decoding theory of Polar code and the implementation of the encoders and decoders for some systematic Polar codes are studied.Firstly,the channel polarization of Polar code is analyzed and studied in detail,the expression of channel transition probability is deduced.Four kinds of estimation for the channel reliability sequence are discussed,which are Bhattacharyya Parameter method,Density Evolution method,Gaussian Approximation method and Polarization Weight method,and the performance of these methods is simulated and compared.The structure and properties of generating matrix are analyzed,the encoding principle of systematic polar code and the transformation method of bit mixing sequence for hardware implementation are given in this thesis.Based on the theory of polar code encoding,the encoding process of non-systematic polar code and systematic polar code is explained.The performance comparison between non-systematic polar code and systematic polar code shows that the systematic polar code is of better performance under the same E_b/N₀ conditions.Secondly,the Successive Cancellation decoding algorithm of Polar code is studied.By means of the code tree constructed by polar code,the decoding process of SC decoding algorithm,together with its application to the decoding of systematic polar code is explained.Two kinds of decoding structure of polar code are analyzed,including recursive decoding structure and non-recursive decoding structure.It is found that the non-recursive decoding structure is more suitable for hardware implementation.Based on the non-recursive decoding structure,a unique level processing method is given to simplify the decoding process.Several kinds of the derivative decoding algorithm based on SC decoding algorithm are studied,including fast SC decoding algorithm,Successive Cancellation List decoding algorithm and Cyclic Redundancy Check Aided SCL decoding algorithm.Then the performance of these decoding algorithm is simulated and analyzed by Matlab.Finally,the FPGA hardware implementation structure of the systematic Polar codec is proposed.This codec adopts level processing,which can flexibly adapt to different code lengths by increasing the processing level.Nodes of the same level share storage space,saving a lot of storage resources.The core processing module in this codec can be used to construct the SCL decoder,that is,to reserve multiple decoding paths by instantiating multiple computing modules.The implementation environment of the encoder and decoder are briefly introduced in this thesis.The encoding and decoding algorithm of the systematic polar code is simulated under fixed point data structure,and the fixed-point scheme used in FPGA implementation is determined.From the top module architecture to the realization of basic functions,the design idea of codec is explained step by step.Combined with fixed-point simulation,the encoding and decoding function of the codec is verified.According to the number of clocks consumed in the decoding process and the highest frequency of the working clock supported by this codec,the throughput of a single core processing module is estimated to be more than 10Mbps.Combined with its resource consumption,the designed systematic polar codec can achieve satisfactory throughput when the resource consumption is less than 1%of the available resources of Virtex 7 690t FPGA chip.In addition,the relatively low resource consumption makes it more scalable for the designed codec,which is that one can easily obtain a Polar codec with more than 1Gbps throughput only by introducing more SC decoding(or encoding)core to increasing the parallelism.