The Design And Implementation Of AVS 3D Real-time Decoder

Stereoscopic video can provide depth information and a richer viewing experience to the viewers, also it has great value in both scientific and commercial fields and plays a much more important role in the digital video field. AVS is the abbreviation of audio and video coding standard, it is the second generation codec standard in China. Right now, AVS group formulates two core techniques: inter-view prediction and enhanced stereo packing coding based on three-dimensional video. This issue is a branch project of the AVS 3D HD codec standard which is hosted by Ministry of Industry and Information Technology of the People’s Republic of China. The main task of this issue is to complete the development and design of 3D video decoder module.In this paper, we adopts enhanced stereo packing coding algorithm to implement the AVS 3D real-time decoder design. At the encoder side, the stereoscopic video is captured by two cameras whose base-lines are parallel. Based on the correlation between the left view and the right view and each view’s time and space correlation, we jointly encode the left and right view video into one bit-stream. At the decoder side, some new modules should be added to the traditional AVS 2D decoder, through the viewpoints separation module to obtain the base-layer images of left and right viewpoints with horizontal or vertical decreased resolution. The inter-layer up-sample filter interpolates the base-layer images of left and right view to recover the enhancement-layer images of the two viewpoints. The two modules work together to decode the AVS 3D ES stream. Also some works has been done to check the validity of the software design.Then we use hardware acceleration module to parse the syntax element. There are Exp-Golomb and CAVLC two ways to do so in AVS standard. Exp-Golomb is the abbreviation of exponential golomb coding; CAVLC is the abbreviation of context-based adaptive variable length coding. The FPGA hardware acceleration module is used as one part of the SoC 3D decoder system, also the interface of the hardware acceleration module and the SoC 3D decoder system has been implemented.In the end, we use Xilinx ZYNQ 7020 development board as the SoC platform. ZYNQ 7020 is a SoC system which has two internal M9 processing system hardcore chips. It has some advantages such as high level of integration, strong control ability and good software commonality. We use one master M9 as top-level control system to complete the external interface communication with the 3D ES stream and the display of the decoded images; the other slave M9 and some hardware acceleration modules work together to complete the stereo-packing decoding algorithm; the two M9 s cooperate to implement the design of AVS 3D real-time decoder based on FPGA/SoC platform. At last, by means of HDMI port, we export the decoded stereoscopic video including left and right view data to the 3D display device. Through the viewpoints interlacement, we can get the 3D video with disparity information and verify the validity of the design.