Method Of Design For Testability Optimization With Unreliable Test Of Board-level Circuit

With the electronic equipment system becoming more and more complex, it is particularly important that we check and repair the fault electronic system quickly. It requires the design for testability at the beginning of the design of the system to facilitate the maintenance of the system. However, due to the unreliable test in the process of diagnosis of board-level circuit, test result is not always completely accurate. Taking no account of these situations, the current method of design for testability based on reliable test has some limitations. Considering the shortage of the current methods, this paper introduces a method of design for testability with unreliable test of the board-level circuit. The mainly research result is as follows:(1) Based on the characteristics of the board-level circuit test, a dependency matrix of component’s fault models and test is constructed in this paper. According to this matrix, this paper proposes a calculation method for the testability index with the unreliable test. Two aspects are considered, component-level and pin-level.(2) In the testability optimization analysis with unreliable test, this paper presents test optimization selection algorithms and test sequencing algorithms. Problems for test selection, the paper presents two kinds of improved optimization algorithm. The first one is based on grouping coding genetic algorithm, which is for the index constraint under each process at the board-level circuit testing process. This method is much higher than the overall coding optimizing method in efficiency. The other is heuristic particle swarm algorithm, which is for the index constraint under the whole testing process. Compared with the traditional greedy algorithm, this method reduces the overall cost of testing. This paper introduces AO* algorithm with unreliable test in the test sequencing optimization analysis. Considering the unreliable test factor, the algorithm can reduce the cost of misdiagnosis in the process of searching for the optimized test sequence.(3) At last, the paper proposes a method of testability modeling of board-level circuit with unreliable test. Fault_test dependency model can be constructed by putting the component information, fault mode information and test information into the database. Meanwhile, the methods of calculation of the testability index and testability optimization are integrated into the testability analysis software. The software will be applied to Huawei’s testability analysis of board-level circuit.