Design And Development Of NS1066 Production Test System

With the development of integrated circuit design and manufacturing process to improve the performance of hard disk USB3.0 to SATA bridge chip increasingly high integration complexity chips are also increasing.In order to ensure the yield of the chip,increasing the internal signal observability and controllability,how to improve the testability of the chip have become difficult problems in the study.Also,because USB3.0 to SATA bridge chip hard disk expanding range of applications,software application development difficulty also increases late,so the introduction of design methods can debug SATA hard bridge chip design process,which can be hard bridge chip complex application development to provide effective support.To solve the problem of chip testing and debugging software development late,in-depth study of this paper basis USB3.0 to SATA HDD bridge chip architecture,combined with the design for testability method for on-chip debugging techniques and applications,designed based on JTAG the hard disk bridge chip boundary scan protocol chip debug system.The debugging system includes TAP controller,instruction register,the data register,boundary scan chain,on-chip debug unit and breakpoint register set and other modules.Host chip through JTAG interface for debugging,control pipeline pause,run,the realization of the chip core observation status and settings,complete set of read and write operations within the chip registers,while design and implement software and hardware breakpoints,single-step control and other basic debugging features;within the designed chip debug system does not require the addition of new pin on the chip,can be achieved only within the board-level boundary-scan test and on-chip debug function via on-chip necessary Ding TAG interface.On this basis,completed the hardware design debugging system,conducted a test program code description,simulation,program verification and load board design.Validation results show that the debugging system can be completed well within the chip-chip debug function to meet testability and debugging of demand for load board-level testing and post-application development provides the foundation.