| As the density, complexity, and speed of VLSI circuits continue to increase, it has become apparent that chip-to-chip interconnections can limit the overall performance of an integrated electronic system. High performance electronic systems require closely packed chip-to-chip interconnections in order to obtain shorter interconnection length and to accommodate the large number of I/O pads of VLSI chips. The smaller interconnect pitch gives greater signal attenuation, crosstalk, and dispersion per unit length. Therefore, we have a complex trade-off between signal delay, losses, crosstalk, dispersion, reflection, characteristic impedance, and spatial density.; Here we discuss the analysis of lossy interconnections as long transmission lines whose cross-sectional dimensions are on the order of several micrometers. A proposed two-level interconnect structure appears to offer an attractive combination of high-speed (c/1.8), low crosstalk (less than 5 percent over 10 cm), low loss (0.05 dB/mm at 1 GHz), high density (35 {dollar}mu{dollar}m pitch), and can operate at frequencies exceeding 1 GHz. The fabrication process of the structure and experimental results are presented.; To reduce skin effect losses at high frequencies microstrip/strip lines with laminated conductor and dielectric layers can be used. Laminated transmission lines can operate without skin effect loss and high frequency dispersion for frequencies as high as several tens of gigahertz.; The anticipated propagation characteristics at 77K of superconducting transmission lines using the new high critical temperature superconductor Y-Ba-Cu-O are analyzed and an accurate transmission line model drawn up.; Finally, switching noise and its susceptibility in system-level integration are analyzed. Various approaches to reducting of switching noise are discussed including a new packaging scheme and self series terminated low voltage swing CMOS buffers. |
