The Implementation Of Viterbi Decoder By Using FPGA

With the development of communication technology and information technology, the reliability and validity of information transmission are more and more required. As an important part of digital communication system, channel coding technology is play an important role in digital communication for ensuring communication reliability, and it has widely used in anti-jamming and error control in digital communication.Channel coding include block code and convolutional code. Convolutional code is widely used in wireless communication systems and satellite communication systems as its good performance. Viterbi decoding algorithm is a kind of maximum likelihood decoding algorithm of convolutional coding, which has coding efficiency and speed advantages, and it has been considered as the best decoding algorithm for its advantages of good decoding performance and high speed. Convolutional code and Viterbi decode is widely used in forward error correction of communication systems.With the development of programming logic technology, the implementation of the Viterbi decoder based on FPGA becomes more easier.The main contents of this paper is to implemente a Viterbi decoder which has constraint length 9 and code rate of 1/2.In this thesis, the theory of convolutional code and the description of convolutional code are firstly introduced.And then the principles of Viterbi algorithm and the key factors which decide the decode performance are explained. Finally highlighted the Viterbi decoder modules of various algorithms and methods used in this design as follows:1.In the branch metric generate unit,the input symbol is represented as 3-bit code being level 8 quantified.The algorithm of the Euclidean distance is simplified ,so the compute of branch metric can be easily implemented by hardware circuits.2.In the add-compare-select unit, through the comparison of the three implementations, I choose serial-parallel method as it can meet the decoding speed while saving chip resources.3.In the path metric memory unit, I use Ping-pong mode , as this method is straightforward and the control circuit is simple。 4.In the survival path memory unit,we use trace back method instead of register exchange,because it can reduce the complexity of the implementation while use less registers.Finally, based on the research of the Viterbi decoding algorithm, I completed the design of Viterbi decoder by using Verilog hdl language in Altera's Quartus II integrated development environment, In order to verify the correctness of the design, I also designed a simulation platform, and verified the decoder by using Modelsim, which is the industry's popular simulation tool.