The Design And Implementation On Viterbi Decoder Of Punctured Convolutional Code

In digital communication system,especially a wireless communication system based on the IEEE 802.11 ac standard,punctured convolutional code and Viterbi decoding algorithm are important techniques for improving reliability of information transmission,which have important research value.As people's requirements for data transmission rate are further increased,the complexity of their hardware devices is also increasing,while the complexity of decoding,hardware system power consumption and resource consumption issues of the Viterbi decoder of punctured convolutional codes have restricted its further development and application in digital communications.Based on the IEEE 802.11 ac standard,this thesis aims at reducing the computational complexity of the algorithm,the system power consumption and hardware resource consumption in the hardware design.It improves channel coding and decoding algorithms(including binary convolutional code,interleaving,and scrambling algorithm).On the basis of completing the algorithm design,hardware modules are designed for channel coding module.In order to solve issues of the high power consumption and high hardware consumption of traditional design methods,optimization schemes are proposed.The main research results of this thesis are as follows: 1.The Viterbi decoding algorithm for punctured convolutional codes has high computational complexity at high code rates.In order to solve this problem,an improved Viterbi decoding algorithm is proposed.For the case that with the increase of the code rate,the decoding complexity is also increasing.The introduction of adjustment factors in the algorithm can effectively reduce the steps of calculating the branch metric when the code rate is greater than 1/2,thus greatly reduce the complexity of decoding.Through the establishment of the orthogonal frequency division multiplexing system loop,the bit error rate performance of the system can be evaluated.2.With regard to the problem that the complexity of decoding hardware design of puncturing convolutional codes increases with increasing code rate,it is proposed to add registers for storing puncturing position indication information during the hardware design process.It is used to indicate whether the position is zero-padding data.When the branch metric value is calculated,the information of the register is compared with the calculation result of the metric value.And the result of the input metric value of the Add-Compare-Select module can effectively reduce the complexity of the Viterbi decoder for calculating the branch metric value.Based on the FPGA platform,the hardware design can be verified by Quartus II software and the SignalTap II online logic analyzer;3.For the problem of low efficiency and large system delay of the Viterbi decoder for punctured convolutional codes,four Add-Compare-Select sub-modules within the Add-Compare-Select module in decoder are designed.It uses parallel synchronous operation,which can effectively improve the system decoding efficiency and reduce the decoding delay;4.For the imbalance between the hardware resource consumption,system power consumption and codec performance in the hardware design of channel coding,this thesis presents a combination of serial and parallel hardware design methods.The channel coding transmitter adopts full parallel and combinational logic for hardware design.Compared with the traditional serial processing method,the system power consumption can be greatly reduced.The channel coding receiver adopts a combination of serial and parallel processing methods.Double-clock 250 KHz and 20 MHz are adopted to deal with hardware resource consumption and system power consumption issues.The de-interleaving module,zero-padding module and anti-scramble module at the receiver adopt a parallel processing method.For the decoding module,an input/output string and parallel conversion interface are added.The method reduces the resource consumption in the hardware design while effectively reducing system power consumption.Layout design based on Magnachip's 0.18?m CMOS crafts can be used for chip verification.