Design And Implentation Of Viterbi Decoder In UWB On FPGA

Being a wireless radio communication technology suitable for short distance communication, UWB (Ultra-Wide Band) adapts ns pulse signal width with GHz signal frequency spectral and lower signal power. It becomes a hot point in the wireless radio communication area for its high distinguishability, high intercepting ratio, more information content and detection ability on concealment. It is a key point to lower the error rate of transmission data in order to improve the reliability of communication. UWB system adapts the IEEE 802.15.3 protocol which employs a (2,1,6) convolutional encoder and maximum likelihood Viterbi decoder in channel coding scheme when transmiting signal data.Firstly, the basic concept and development of UWB technology at home and abroad is introduced in the thesis. Specifically for the channel characteristic of UWB, traditional error correct scheme convoluntional coding and Viterbi decoding is adopted, error correct capability and FPGA design is analysed.Secondly, consulting IEEE 802.15.3 protocol, a (2,1,6) convolutional encoder and its Viterbi decoder is implemented, applying serial mode, trace back decoding, dual RAM storing path metric and surviving information to fufil timing requirement. The circuit is described by Verilog Hardware Description Language, front simulated in Modelsim and after planning and routing synthesized in Quartus II. Soft decision information generated from Matlab simulation platform resolves the difficulty of generating it.The thesis shows the simulation results of modules.Finally, the (2,1,6) Viterbi decoder circuit is verified in Cyclone II FPGA, the result shows that it works well and its system clock frequency is 44 Hz fufiling the requirement of UWB channel coding. Compared with parallel mode, this scheme saves about 75% resource.