An Optimized Design Of Fast Floating-point Adder

With the development of multimedia and the computer science, floating point unit integrated in the central processor as the core arithmetic unit becomes the current processor's essential feature directly. There are massive needs for highly and effective floating point calculation in the 3D video processing, the speech recognition, as well as the project operation. As the time developed, in many domains, the floating number operation is playing more and more important role. Especially in the high speed real-time digital processing aspect, the peoples'needs for the high performance of floating point Unit (was called FPU) have been more urgent, thus the design of FPU became one key components in central processor design.The floating point additive operation is the one which is used most frequently in all the floating point instruction. According to the Oberman statistics, the floating point additive operation has taken above floating point calculation 55%. Because the floating point addition's using frequency is the highest and the design is the most difficult, therefore the design of floating point adder becomes to be a very essential part in the modern microprocessor and the digital signal processor most greatly, it's performance immediate influence CPU floating point calculation ability.In this paper,we use the Top-down designing method, first introduce the traditional 5 cyclical floating point addition algorithm , then make the improvement regarding its step analysis, use the Two-Path algorithm. This has constructed in the floating point algorithm basic mentality as well as each basic module constitution, we present a new design of IEEE compliant double precision floating point adder by using various optimization techniques,such as two data path separation,three pipeline stages,fastest 53bit CLA adder, a new LZA logic for high-speed floating- point adder, using barrel shifter,and simplify the rounding.All of above measures could effectively increase the speed of floating-point adder unit, then we use EDA tools to do verification and synthetizition. The verification is from down to top, from small to big, and from easy to complex. For the purpose to find whether the design is right or not. After verification, the adder could achieve high performance up to 350MHz, and could save 23% logic gates compare to traditional algorithm.In the end of this paper, We make a summary of the design including insufficiency and propose the forecast improvement.