Research On Reconfigurable Architecture For Parallel Low-level Vision Computing

With respect to system realization, this dissertation proposes a design frame for low-level vision computing system, which involves the considering of parallel computing and reconfigurable computing. This framework is built on a large amount of analyses of data flow of vision algorithms. To map algorithms with similar feature onto the corresponding architecture based on data flow,this paper presents a formal representation of algorithm data flow feature and proposes a DPMC model for data flow analysis. According to the analyses, low-level vision algorithms are to be classified into four types, and vision computing is divided into three levels: data processing level, task-information level and analysis-interpretation level.To test the proposed design frame and multi-level division, this dissertation then designs a reconfigurable parallel system, which supports hierarchical computing, to realize those suppositions in the background of vision navigation. To improve the capability of parallel accessing in the designed system, we give a memory architecture which supports neighborhood parallel accessing; to offer a flexible interconnection environment between PEs or between PEs and memory system, we design a reconfigurable interconnection network based on FPGA, and give the concrete design method and steps.