The Research And Stduty Of The Hardware Architecture Of A Reconfigurable Heterogeneous Multi-processor System On Chip

In the past half a century, Moore's law provides a clear direction for the development of semiconductor industry. Namely, reducing the feature size of CMOS circuit improves its performance. Limitted by the physical condition, the feature size of the existing CMOS digital integrated circuit technology cannot be unlimitedly shrinked. In addition, the frequency of the CPU cannot be unlimitedly rised because of the dynamic power consumption. As a result, the performance of the CPU cannot be improved by shrinking the feature sizes and rising the frequency without limitation. CPU performance and energy efficiency should be improved through the new material, new structure and new devices. Therefore, a new architecture is proposed in this paper.At present, the hardware accelerators such as GPGPU, FPGA have been widely used in the engineering project. However, the programming model of the GPGPU usually is binding with the hardware. This makes the programming models cannot be extended to the heterogeneous systems. In addition, the energy efficiency and performance are lower that the FPGAs. As for the FPGAs, they are too difficult for the programmer to develop the applications.In order to solve this problem, HOCR-MPSOC, an architeture that combines the chraracteritics of the hardware programmable FPGA with OpenCL heterogeneous computing standard is proposed. The host of the whole system is Microblaze processor. The modules of the system are connected on chip by AXI4. Throgh this bus the OpenCL slave device and the peripherals are able to be driven by the host. Each Open CL slave device is called a compute unit.In this design, OpenRisc1200 is dedicated to be the computing core, conncted with other digital circuit modules through WISHBONE inside the compute unit. And there is an AXI4-WISHBONE connect bridge to make the whole compute unit be the slave decice of the host. The advantage of the heterogeneous structure is the organization of the different feature of the processing cores. Based on this kind of structure, the host can schedule the different cores to work in a parallel and optimized way according to the different computing task in order to achieve optimum processor core resources configuration and maximum performance.There are two advantages of the HCOR-MPSOC. Fisrt, HCOR-MPSOC supports the heterogeneous standard OpenCL so that programmer can develop applications easily. Second, HCOR-MPSOC takes the advantage of the FPGA that the enery efficiency and performance are significant.Compared with the I3-2330 CPU and the dedicated IP, the energy efficiency and perfomace of HCOR-MPSOC are identical to the expection according to the exsiting study. Based on HCOR-MPSOC, the developing route of this system has been proposed.