Design Of An Optical Receiver For High Speed Optoelectronic Modulation

With the maturity of silicon-based microelectronics technology,people have stepped into the information age dominated by the electronic revolution.The silicon industry follows the famous Moore's Law,which states that the number of transistors in integrated circuit chips doubles every 18 months.Over the past decade,however,Moore's Law has shown signs of waning.As the limit of chip integration is approaching,the interconnection delay caused by the inherent properties of traditional metal interconnects is becoming more and more important.Therefore,a new structure is urgently needed to solve this problem.From the perspective of large-scale commercial application and technological development,optical communication based on photonic components and photonic integration technology has experienced a long-term evolution from national backbone network,fiber-to-home,inter-device and plate-level fiber interconnection to module level optical interconnection.With the continuous improvement of communication development requirements such as ultra-high speed,ultra-wideband and low power consumption,optoelectronic fusion integrated information network has become a major technology development trend.The development of core technology begins to focus on the optoelectronic integration at the chip level,which also points out a new way for the interconnection of integrated circuit on chip.In this paper,based on the optical detector module with the Avalanche Photon Diode(APD)as the core and the front-end analog circuit module with the Transimpedance Amplifier(TIA)circuit as the main part,an optical receiver package chip which can be used in 10 Gbps optical communication system is designed.In the photodetector module,we analyzed the photodiodes with different structures and finally decided to adopt the standard APD chips for domestic commercial use,and put the main design focus on the 10 Gbps TIA amplifier circuit.There are two technological approaches in chip technology,SiGe and CMOS,which have great differences in parameters and performance parameters.At present,several TIA products launched at home and abroad are developed based on SiGe technology.Compared with SiGe technology,CMOS technology has differences in key parameters such as noise,gain,bandwidth,linearity and operating voltage.However,CMOS technology is the most mature technology in today's electronic industry,and CMOS chip has the highest chip integration and the lowest production cost.Therefore,based on the 40 nm CMOS process,a high-speed TIA chip with a speed of 10 Gbps is designed in this paper,including cross-resistance amplifier,intermediate differential amplifier and output buffer circuit.When light input capacitance for 250 f F,the equivalent input noise current of 15.5 pA(Hz)^1/2 on average,3 d B bandwidth 8.5 GHz,66 d B ? transresistance gain,the encapsulation chip simulation results completely in line with expectations,good figure test eye open canthus.The chip area is 100?m^*110?m,without inductance peaking technology,which greatly reduces the chip production cost.