Design Of Network-on-chip For Homogeneous Multi-processors

As the development of IC technology, the processing resources on a single chip become more and more. Because of the relationship between power and performance, those processing resources are more and more likely to be divided into many small cores, rather than several strong cores. Also, in Deep Sub-Micro (DSM) process, global wires face delay and driving loads problems, thus the conventional bus interconnection becomes unsuitable for future System on Chip interconnection.Network on Chip adopts data packet switching and routing techniques on a single chip, and was designed for many IP cores interconnection. NoC has advantages of extensibility, regularity and modularity. Along with the 3D IC's development, it becomes a widely researched topic.After designing a network adapter for a NoC, This thesis first established a network-on-chip connected multi-processor system, and then researched on how to avoid that the memory becomes performance and throughput bottleneck.We applied the Distributed Shared Memory architecture on NoC connected Multi-processor, and did some optimization in software way. This design had showed improvemence of performance and throughput in a final muti-threaded benchmark.