Research On Key Technology Of High-efficient Shared Memory System In Network Processor Based On MPSoC

The memory performance falls far behind the processor, known as"the memory wall", becomes the bottleneck of high-performance multi processor system. Network processor, a device with flexibility like RISC processor and high speed comparable to ASIC, has gradually become the basic network system components. It represents the future development direction of network equipments.The dissertation derives from the National Science Research Project of research on and design of high-performance network processor. According the various requirements of look-up table and forwarding table for processing speed, this thesis systematically analyzes the characteristics of different memories, and propoesed a on-chip shared memory control system. Command queues are designed respectively for SRAM and SDRAM controller, together with the hierarchical priority arbitration mechanism, multiple processors effectviely accessing the memory parallelly is attained.With the mutual exclusion Mechanism based on of the principles of CAM, named as locking CAM, processors can lock the memory address to prevent other processors from modifying the contents of the address. Therefore, multi-processor coordination is achieved when accessing the memory, and data security is ensured.The general access for the SDRAM includes operations such as row activation and precharge, which consume more than half of the memory accessing time. This paper further proposes Consecutive same row optimization and Pingpong optimization. These optimizations can respectively eliminate row activation and precharge operations or hide the prechareging time during memory access.Through the Simulation and Verification Platform Based on network processor, locking CAM's functions like locking and unlocking address are proved to be correct and effective. And simulation and verification of controoler's functionality and performance results show that memory performance improves maximally by 56% compared to pre-optimized, making it meet the high throughput requirements of shared-memory controller in MPSoC.