Research On Low-power Oriented Shared Memory For Multi-core Systems

With the continuous development of technology, demands for computing are increasing, which makes multi-core processor on chip has become the mainstream. However, with more cores integrated into a single chip, the DRAM memory design faces ever increasing challenges. As the system raise higher demands on the memory capacity, working frequency and bandwidth, the memory power consumption increases more rapidly. It is shown in a recent study that memory system power consumption are close to or even greater than that of the processor, which can consume up to 40% of the system power. DRAM power consumption is the main factor constraining the whole system's growth in performance. Moreover, memory accesses from different threads are usually interleaved and interfere with each other, which further exacerbate the situation in memory system management. Therefore, reducing memory power consumption and improving the performance has become an urgent problem to be solved in both academia and industry.This paper analyzes the current situation of optimization scheme on shared memory in chip multi-cores. We find most schemes focus on improving the performance, maximizing the fairness and reducing the power consumption. However, most studies reduce the power consumption on the base of reducing system performance or fairness. Single improvements like cask theory cannot really solve the problem. Although Moore's law pushes the continuous improvement of the processor structure, the memory wall problem still exists. At the same time, the problem is becoming more serious with more cores integrated on the chip.For the above, in order to improve the system performance and reduce the memory power consumption simultaneously. In the first part of my paper, we propose a new mechanism called Dynamic Bank Partitioning(DBP), which allocates Banks to different threads based on their memory access characteristics. DBP not only effectively eliminates the interference among threads, but also fully takes advantages of Bank level parallelism and spatial locality. To save Banks, DBP does not allocate dedicated Banks for threads with low memory intensive. Instead, DBP gives the priority to these threads they can access all Banks evenly. Because such threads only generate a small amount of memory accesses, and their propensities to cause interference are low. For memory intensive threads with low row-buffer locality, DBP balances spatial locality and Bank level parallelism. While for memory intensive threads with high row-buffer locality, DBP isolates their memory accesses from other intensive threads to reserve spatial locality. In the second part, in order to further reduce the memory power consumption and improve the performance, we put forward Bank partitioning based adaptive page policy. First, we use Bank partitioning to isolate memory streams of different threads, and reduce the inter-thread interference. Second, we put forward an adaptive page policy to dynamically allocate the optimal page policy for each Bank.In order to measure the performance and memory power consumption accurately, we evaluate our proposal using gem5 as the base architectural simulator, and integrated DRAMSim2 to simulate the details of DRAM memory system. We use workloads constructed from the SPEC CPU2006 benchmarks for evaluation. Experimental results show that DBP can reduce memory power consumption up to 21.2% and 10% on average across all mixed workloads. In the meantime, DBP improves the performance up to 12.5% and 3% on average. In the case that workloads are built with non-intensive applications, our scheme reduces the power consumption by 5.3% averagely and improves the performance to some extent. Compared with the unified open page policy, adaptive page policy improves the system performance up to 55% and 20.4% on average, which reduces DRAM power up to 29% and 8% on average for all workloads. So DBP and adaptive page policy achieved a better balance in terms of low-power and performance.