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Modeling Of Shared Cache Memory Access Behavior Based On Artificial Neural Network

Posted on:2019-01-12Degree:MasterType:Thesis
Country:ChinaCandidate:C HuangFull Text:PDF
GTID:2428330590975489Subject:Integrated circuit engineering
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With the rapid development of electronic information technology,the chip multi-processor(CMP)has been become the development trend of modern high-performance processors.The cache,as an important bridge between processor and main memory,plays a crucial role in the optimization of performance of computer architecture system.The shared cache in multi-core processors as an important factor affecting processor performance,has been increasingly regarded by the industry and academia.Hence,it is significant to create a model that can analyze and predict the access behavior of the shared cache,which is of great significance for the cache architecture design and software performance optimizations.This thesis focus on studying the shared cache behavior model and find that prior works have ignored the influences generated by the instruction and data conflict behaviors,in which this thesis aims to establish an analytical model for predicting cache behaviors in the instruction and data shared cache.The main contribution of this thesis contains two parts.Firstly,this thesis adds extra codes in the gem5 simulator and provides the method to extract the program reuse distance histogram,with which the reuse distance histogram on the multi-core shared cache can be calculated with CPI.Secondly,prior works over-simplified the real target architecture and application scenario,in which the precision is severely degraded due to the ignorance of conflict behaviors caused by instruction and data caches.Therefore,this paper constructs an artificial neural network(ANN)model to eliminate the effect and improve the prediction accuracy of the shared-level cache behaviors.This model is fed with the reuse distance histogram of the shared-level cache obtained in the first part while the output is the number of shared cache hits.This thesis uses Mobybench 2.0 benchmark suite to evaluate the accuracy of the ANN model.Compared to gem5 cycle-accurate simulations,the ANN model has an average error less than 20% and the minimum error is about 12.8%,which is 25% higher than prior works.In terms of time overhead,the prediction process can be sped up by 55.65% contrast to gem5 cycle-accurate simulations.
Keywords/Search Tags:chip multi-processor(CMP), shared cache, reuse distance, artificial neural network (ANN), instruction and data shared cache
PDF Full Text Request
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