The Implementation Of High Speed FIR Filter

FIR(Finite Impulse Response) filter is widely used in digital signal processing field due to its linear phase, accuracy and easy to large scale integration. In the system of digital signal processing, the request of precison and speed is more and more stringent, so it is an important subject of study to design optimum FIR filter for systems presently.This paper profoundly discusses the basic theory and implementation of FIR filter, and focuses on the two major issues which are the precision and speed in the process of hardware implementation. Firstly it discusses three basic structure of FIR filter based on its theory, and propose a rule of choosing filter structure according to the practical requirement. Secondly, this paper addresses the optimization algorithm about precision and speed according to the choosed multiplier and adder structure to meet the requirements of digital filter's precision and speed. At last, the basic multiplier and adder are designed in this paper.The optimized techniques in this paper consist of two aspects: one is the algorithm optimized for the coefficients of filter, the other is the structure optimized for implementation of filter. The first include two major technique, they are finite word length effect in the process of coefficient quantization and CSD(Canonic Signed Digit) encoding, the second include two phase filter structure, Wallace Tree multiplier, error compensation to truncated multiplier and elimination of signed extension.According to the aboved optimization algorithm, this paper determinate the bits length of this filter's coefficient in the process of quantization, and then make a CSD encoding to the coefficient. In the process of hardware implementation, this paper adopts the Wallace Tree multiplier and carry lookahead adder as the basic cell to improve the calculation velocity of the digital filter. Additionally, the K-J Cho approach and elimination of signed extension can effectly compromise accuracy, speed and area of the FIR filter.Finally, this filter has been verified comprehensively, the results of simulation indicate that the design is correct. Additionally, the DAC chip has been taped out successfully which adoped this FIR filter as 2x interpolation filter.