Design Of High Speed Digital Image Acquisition System Based On FPGA

With the development and application of the embedded image processing system, the front-end image collection system has caused serious concern. It determinate the resolution ratio and accuracy rate of the subsequent design. The video image acquisition should be high speed, high integration, high-resolution and high reliability to meet market demand. It has a widely use in industrial, military, medical, image acquisition system, for example, in the video phone,image recognition, video conferencing, monitoring system, industry control, remote monitoring.FPGA's rapid development provides a new solution for image acquisition and pr-ocessing system. This paper describes the application and research status of image acquisition system. Compare advantages and disadvantages of DSP, ASIC and FPGA in image acquisition and processing system, proposed a FPGA-based image acquisition and processing system. The whole system is divided into five major functional modules, there were image acquisition module, image storage module, image display module, FPGA core processing module and peripheral achieve module. Select chips and design the hardware circuit. Including image acquisition circuit, D/A converter circuit, SDRAM interface circuit, VGA interface circuit, clock circuit, JTAG interface circuit and power supply circuit. The chip's logical control, peripheral interface logical control and data processing algorithm are all realized by FPGA.This paper discussed EDA tools, and designed of image collection system function module structure. Do the module simulation in Quartus II software platform, the simulation results have proved that the correctness and feasibility of the system design. These modules mainly includes:the CMOS timing driving module, Serial data string module, SDRAM literacy control module and image preprocessing module. In the pretreatment modules, three image preprocessing algorithm simulated by Matlab, the hyperbolic approximation algorithm proved to meet the design requirements. Finally a new deconvolution algorithm is proposed based on the characteristics of CycloneⅡchip.