Research On Device’s Model Of Polycrystalline Silicon Thin Film Transistors

The display technology plays an important role in the daily lives of the human beings. As the active device, polycrystalline silicon thin film transistors have been widely used in the active-matrix liquid crystal displays and active-matrix organic light-emitting diode displays since they have the high mobility and are flexible to realize the integration of the driving circuits. The device’s model for polycrystalline silicon thin film transistors is the key issue in the circuit design. It is helpful in circuit simulations, predicting the performance of the circuits and reducing the cycle of the research. And it will benefit the circuit design. The accurate and effective compact model for polycrystalline silicon thin film transistors is needed in the circuit simulation. Meanwhile, the new generation compact MOSFET model adopts the surface-potential-based model structure. So the calculation of the surface potential is very significant. Therefore, in this dissertation, the surface potential model is first studied under the one-dimensional analysis and the quasi two-dimensional analysis, respectively.Moreover, concerning about the real application conditions of the device in the circuit, the reliability model for polycrystalline silicon thin film transistors needs to be studied. It is helpful in better understanding the devices’degradation and failure mechanisms, presenting the gist for the circuit design and improving the performance of the circuit. According to the practical needs of the engineering, in this dissertation, the off-state current model under the hot-carrier stress for polycrystalline silicon thin film transistors is studied, later, in the field-enhanced-generated off-state current and the thermally generated off-state current, respectively.The main research contents and innovations are as follows:1. Study the surface potential model for polycrystalline silicon thin film transistors under the one-dimensional analysis. The numerical model, analytical model based on different regions and the unified analytical model of the surface potential are derived. And the impacts of the parameters of the devices’model on the surface potential and the surface vertical electrical field are studied. Furthermore, the surface potential model including the interface charges is deduced. The impact of the interface charges on the surface potential is analyzed.2. Study the surface potential model for polycrystalline silicon thin film transistors under the quasi two-dimensional analysis. The approximate analytical model of the channel potential in the strong inversion region under the high gate voltage and the low drain voltage is put forward. Moreover, the surface potential model based on the channel potential in the strong inversion region under the above conditions is deduced. And the surface potential model which neglecting the channel potential in the weak inversion region is obtained. It realizes that one-dimensional model approaches the surface potential in the two-dimensional device. And the impacts of different gate voltages, drain voltages and channel lengths on the surface potential under the above two conditions are studied.3. Study the field-enhanced-generated off-state current model of hydrogenated metal-induced laterally crystallized n-type polycrystalline silicon thin film transistors under the hot-carrier stress. It is found in experiments that the field-enhanced-generated off-state current is affected by both the "drain electrical field reduction effect" and the "flat band voltage shift effect" under the hot-carrier stress. And the relationship between the field-enhanced-generated off-state current and the P-F model is put forward before and after stressing under the theoretical analysis.4. Study the thermally generated off-state current model of metal-induced laterally crystallized n-type polycrystalline silicon thin film transistors under the hot-carrier stress. The phenomena of the decrease and increase of the thermally generated off-state current under the hot-carrier stress are observed in experiments. Later, under the theoretical analysis, several conclusions are put forward. (1) The thermally generated off-state current is affected by both the "depletion region modulation effect" and the "trap increase effect". (2) The "depletion region modulation effect" is the dominant mechanism, occurring under the larger stress-Vd or with the larger devices’size. (3) The increment of the thermally generated off-state current relative to the initial one follows the Schottky model in the forward mode.