Research On The Performance Improvement For RISC-V Microprocessor

High performance,low power and high reliability have become the development trend of microprocessor.On one hand,high performance has always been the dominating research direction of microprocessor design.On the other hand,low power and high reliability design methods will cause a certain degree of performance loss to the microprocessor.How to implement the low power design and high reliability design with less timing cost have also become a key issue in microprocessor design.In recent years,the open source and free RISC-V instruction set has been paid extensive attention from the academia and the industry.The research on performance optimization methods for RISC-V microprocessor has important engineering practice significance.This paper takes Rocket processor as the research prototype,which is based on RISC-V instruction set,and studies the performance optimization methods for RISC-V microprocessor from the aspects of high performance design,low power design with low overhead and high reliability design with low overhead.Firstly,the architecture of Rocket prototype processor is studied.Next,a high-speed floating-point unit for RISC-V processor is designed.Then,based on the number of critical paths and sensitivity,a multi-threshold low power optimization algorithm with low performance overhead and significant leakage power reduction is proposed.Finally,this paper proposes a Self-Adaptive Dynamic Checkpoint(SADC)algorithm with low performance overhead and low parameter sensitivity based on the adaptive failure prediction.The specific research contents and results of this paper are as follows:(1)The user instruction set,privileged instruction set and coding space of RISC-V are summarized.The architecture of Rocket processor based on RISC-V instruction set including the overall architecture,pipeline architecture,interrupt architecture,and Rocket Custom Coprocessor(RoCC)interface are outlined.The current problems,challenges and optimization directions of the Rocket processor are elaborated.(2)Aiming at the performance optimization requirements of the RISC-V processor floating-point unit,the architecture and problems of RISC-V FPU prototype are analyzed.Based on the algorithm optimization and pipeline optimization,the 4-radix Booth-Wallace multiplication module is designed to replace the original multi-bit wide multiplication module;the parallel leading zero detection module based on binary tree is designed to replace the original serial leading zero detection module;the pipeline stages of some submodules are increased.Based on SMIC 55 nm process,the RISC-V floating point unit prototype before and after the optimization design are verified and evaluated.The experimental results show that the function of the optimized RISC-V floating point unit is correct and its working frequency reaches 820 MHz.Compared with the RISC-V floating point unit prototype before optimization,the operating frequency is increased by 39.46%,but the area overhead increased by 15.14%.The optimization ideas for RISC-V FPU are also applicable to other FPUs.(3)Aiming at the requirements of low power design for RISC-V processors,research on the traditional multi-threshold CMOS(Complementary Metal Oxide Semiconductor)algorithm is conducted.In order to solve the problems of insufficient characteristics when they evaluate the unit replacement priority,high complexity,and insufficient power optimization effects in traditional methods,a multi-threshold low power optimization method based on the number of critical paths and sensitivity is proposed.Experimental results show that under the clock constraint of 10 ns to 16 ns,the proposed algorithm can reduce the static power of the oc8051 processor circuit by 61.16%-62.42%,and the comparison algorithm can reduce the static power of the oc8051 processor circuit by 60.88%-62.42%.Before reaching the highest power consumption reduction ratio,the leakage power reduction effect of the proposed algorithm is always better than that of the comparison algorithm.Under the clock constraint of 5.0 ns to 5.6 ns,this algorithm can reduce the static power of the Rocket Core circuit by 56.60%-59.96%,showing that the power optimization effects are significant.The proposed leakage optimization algorithm is also applicable to any other digital integrated circuits.(4)Aiming at the requirements of high reliability design for RISC-V processors,the checkpoint problem is described,including the definitions,assumptions,and failure types involved in the problem.The traditional checkpoint algorithms are outlined,and the flows of traditional fixed checkpoint algorithm and dynamic checkpoint algorithm are summarized.A self-adaptive failure prediction structure is proposed,and a self-adaptive dynamic checkpoint algorithm is designed based on this structure.The experimental results show that the parameter sensitivity of this algorithm is reduced by 47.69% and 91.98%,respectively,compared with the traditional fixed checkpoint algorithm and the dynamic checkpoint algorithm.The proposed algorithm can effectively solve the problem of high average performance overhead caused by the high parameter sensitivity of traditional checkpoint algorithms.The proposed checkpoint algorithm is also applicable to any other microprocessors.