The Design And Implement Of 32-bit RISC Microprocessor

With the explosive development of integrated circuits, the technology of microprocessor design plays an important role in computer industry, electrical industry and even in the whole information industry. The purpose of this dissertation is to design a 32 bits RISC microprocessor (named IceCore) and to do FPGA prototype verification.Firstly,the microarchitecture is designed based on ISA, and five-stage pipeline architecture which includes IF(Instruction Fetch), ID(Instruction Decode), EX(Execute), MEM(Memory) and WB(Write Back) is adopted. Because the performance of pipeline is determined by hazards, this dissertation uses separated instruction memory and data memory to resolve structure hazard, delay slot where unrelated instruction is write into by compiler to resolve control hazard, and forward data path to resolve data hazard, after analyzing many solutions that are used to resolve pipeline hazards. Both ID stage and WB stage are completed only in half a clock cycle, then branch instructions can efficiently use data which comes from forward data path to avoid data hazard of ID stage.Secondly, IceCore is implemented on Spartan3 device of Xilinx Company for FPGA prototype verification. IceCore has a UART interface, while instruction memory, data memory and register file have a debug interface, so IceCore can communicate with software of PC through RS232 interface, and the verification can be done fast and conveniently.Finaly, the work of this dissertation is concluded and some advices about the further work are proposed.