The Design Of A Programble Divider For WLAN

Driven by the rapid development of the IC industry, wireless communication technology is undergoing large change. Various protocols and applications appeared. WLAN is also development toward the direction of more safety. faster (?)ransmission speed, and better quality. Based on CPPLL frequency synthesizer is one of the basic module in a WLAN RF transceiver, it provides high purity. high frequency, high stability and programmable local oscillator signal.Divider that located in the feedback loop is a critical component of CPPLL. Because divider directly access to the output of VCO, the dual-modulus prescaler is working at the highest frequency, its power consumption takes greater parts of total frequency synthesizer. With the operating frequency of modern communications is going up. its power consumption also increase sharply. Therefore, reducing power consumption is a challenge to RF designer. The contents of this paper are mainly about the low power consumption divider for WLAN.The programmable divider belongs to digital circuit, which consists of dual-modulus prescaler, swallow counters and programmable counters. As the front of divider, dual-modulus prescaler determines its main performance, and become the bottleneck of systerm's optimizing. Firstly, the thesis analyzes the advantages and disadvantages of the various prescalers:Analog mode is difficult to design. Phase switch prescaler is a kind of dual-mode through exchange between different signals with some frequency. It prone to making the glitches during the switch change, it can cause the chaos of logic signal. The traditional structure prescaler is simple, so it isn't easy to fail during working time. Considering the need of the actual circuit, in the paper, we choose the traditional structure. Divider-by-4/5 make up 32/33 dual-modulus prescaler, and design for low-power consumption. Then analysis the working principle of swallow counters, programmable counters and give the circuit structure figure of programmable Divider.Divider-by-2 circuits is the basic unit, the SCL structure was adopted after all structures of analyzing referred above. Then, by a detailed analysis of SCL circuits, we give SCL D latch small signal model and derived the delay formula. Last, giving the optimizing DFF structure..The innovation of this design is in the 32/33 dual-modulus prescaler. We do not pursue high speed for the only goal. but on the based of satisfying the frequency coverage of WLAN 802.(?)la.b reducing power dissipation as low as possible. I sing TSMC 90nm 1P9M CMOS. using Mentor Graphics Eldo for simulation. When the input frequency is 5.8 GHz, the power consumption is only 1.86mW. Finally. based on this dual-modulus prescaler, design the programmable divider meet WLAN 802.11b. The simulation results meet the design requirement.