A Low Power RF CMOS Dual-modulus Prescaler

The remarkable growth of wireless communication systems has caused an upraise in wireless communication protocols , such as GSM ,CDMA ,WLAN, BLUETOOTH ,HOMERF,GPS etc. The raise in frequency range brings an update and improvement in RF integrated circuits.The demand for mobile system cause low power and low cost. The traditional low power RF integrated process is BiCMOS . Along with the improvement of CMOS , we can get RF MOS ,RF inductances and capacitors in CMOS process. The RF integrated circuits design based on CMOS is possible and became more popular.The frequency synthesizer is an important RF front-end part in wireless communication. Its function is change the reference signal, which is low frequency input signal to RF standard LO signal. The frequency synthesizer is a PLL (Phase Locked Loop) in GHz range. The PLL in GHz range is one of the highest power dissipation parts in system . So the decrease of PLL power dissipation will have great effect on the whole system power dissipation.The Prescaler(PS) is a feedback block in RF PLL. The input signal of PS is in GHz range and its output signal is in low frequency range. The PS is one of the great power dissipation parts in PLL . So a low power dissipation PS is important to the PLL.In this paper, the development of situation and technology level of low power CMOS RF prescaler are analyzed and summarized. Also, the theory and methods of low power CMOS RF prescaler are expounded profoundly.In CMOS RFIC design , we focuses on the issue of low power. The main research areas are:1. We complete the macro-structure by digital method .We use digital units such as D flip-flop, logic gats etc. Then analyze and simulate the circuit detailby analog method .We use RF and normal MOS devices in the circuit and do Trans and Period simulation based on analog input signals. Then analyze and adjust some analog references such as DC bias, signal amplitude and noise etc.2. We study some prescaler topology which is conventional structure, analog structure and phase-selection structure. The phase-selection structure have a basic model and two improved models. A 180 degree phase-switching structure has been done which is based on the circuit spec and low power.3. CML ( Current Mode Logic) has been selected . CML logic can reduce signal swing, noise and power dissipation . And CML can be used in high speed analog circuit design . We can design D flip-flop, NAND gate, XOR gate ,buffer etc. The circuit can complete logic function in analog input. We can change the units configuration to fit different request.4. Injection-Locked technique has been used in the first fix divider design. The Injection-Locked Divider (ILFD) model is analyzed . We can mix an input reference signal with the feedback signal. When the output of mixer has a equal frequency with the circuit free oscillate frequency , the circuit oscillate frequency will be locked on it So the ILFD can reduce power dissipation in high operating frequency.The divide-by-16/17 prescaler is implemented in NEC 0.35um RF CMOS technology and Cadence simulation tools. The input frequency is lGHz and the swing is 200 mV. Its power dissipation is 1.6 mW at 3.3V supply voltage.