The Design Of Novel Dual Modulus Divider-by 32/33 Prescaler

The frequency synthesizer is an important RE front-end part in wireless communication. Its function is change the reference signal, which is low frequency input signal to RF standard LO signal. The frequency synthesizer is a PLL (Phase Locked Loop) in GHz range. The PLL in GHz range is one of the highest power dissipation parts in system. So the decrease of PLL power dissipation will have great effect on the whole system power dissipation. The Prescaler(PS) is a feedback block in RF PLL. The input signal of PS is in GHz range and its output signal is in low frequency range. The PS is one of the great power dissipation parts in PLL. So a low power dissipation PS is important to the PLL.In this paper, the development of situation and technology level of low power CMOS RF prescaler are analyzed and summarized. Also, the theory and methods of high-speed and low power CMOS RF prescaler are expounded profoundly.In CMOS RFIC design,we focuses on the issue of low power. We complete the macro-structure by digital method .We use digital units such as D flip-flop, logic gats etc. Then analyze and simulate the circuit detail by analog method. SCL(Source Coupled Logic) has also been selected. In the lower frequency band, DFF with self-latch function were used. This structure not only has locked function but also less MOS transistor than M/S DFF. So it satisfies the command of lower power and noise. The whole system could realize high-speed, low-power, low-jitter.This divider was simulated by Cadence SpectreRF based on TSMC0.18μm process. Results indicate that the divider could operated at 4GHz to realize 32/33 prescaler,and the power was only 4.5mW.