Standard Cell Library Design And Optimization Under Deep Sub-Micron Technology

As the foundation of modern digital circuit design, the Standard Cell library and its performance improvement has tremendous effect on the capability of digital circuit. With chip manufacturing effects from in deep submicron technology, the standard cell layout design as well as the schematic has been largely affected. Recently, the Multi-Voltage Power Domain and Power Gating technique has been induced to meet the demanding of chip power management. All these above are major concerns in standard cell library design and optimization.In this paper, based on SMIC Deep Sub-micron Standard Cell library, the basic introduction of standard cell contents was firstly implemented; in following, many directions and methods of standard cell library optimization have been discussed in this dissertation, including traditional optimizations on multi-threshold libraries, size ratio between standard cells and the PN ratio selection; as well as the deep sub-micron technology STI, WPE effect. With increasing scale of modern digital circuit and the demanding in chip power management, the Power Gating technique was investigated and becomes more and more popular in current digital circuit design. In the last chapter of this paper, besides the explicit analysis in Power Gating technique, an optimization method has been brought in order to provide designers much more choices and balances in Chip Area, Power Consumption and Manufacturing Expense. The upper methods were proved on SPICE simulation and EDA tool analysis, by comparing these two conclusions, the solution has been proposed on the deficiency of Power Gating simulation by EDA tools. This paper systematically introduced and analyzed the optimization methods of standard cell library, thus to provide other standard cell library designers and users better references.