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Design And Application Of Power Balanced Standard Cell

Posted on:2015-09-28Degree:MasterType:Thesis
Country:ChinaCandidate:Q L RanFull Text:PDF
GTID:2308330479479130Subject:Software engineering
Abstract/Summary:PDF Full Text Request
The power attack is the most aggressive、effective and simplest channel attack in cipher chip. Therefor cipher chips have to be analysed in the schematic level to improve power attack resistance. The power balanced circuit is a kind of DPA resistance circuit,however existing circuits is not practical currently. This thesis focuses on the practicability of power balance circuit, and the following contributions have been achieved.1.The power balanced circuit LBDL and SABL suffer higher area and heavier power dissipation, and WDDL cannot be used in real projects owing to poor power balance. Based on the LBDL, we optimized the circuit structure and the number of transistors decreased about 20 percents, compared with original structure. Meanwhile we also provided relative auxiliary circuits.2.The MSDDL FF is not efficient for its larger area and higher power dissipation and the SDDL FF achieve poor performance on power balance. Morever, the two circuits do not support set and clear function. To address above problmes, we proposed a new power balanced flip-flop, TSCSDDL FF, with set and clear. The area decreased about 50 percents and the averger power is saved about 60 percents. Moreover we achieved 2x performance enhancement and the circuit shows better balance with symmetric structure. This circuit has been patented.3.We design the power balanced standard cell library with 65 nm technology. And two layout designed methods “transverse symmetry” and “apart symmetry” were proposed. For the sake of practicality, we achieved 30 power balanced standard cells with 1x, 2x, 4x driver. Finally we used above standard cells to design a power balanced counter with enable port, and verifyed the correctness and power balance by Hspice.4.Aiming at the practicailiby of proposed standard cells, we designed two same counter circuits with power balanced standard cell and 65 nm standard cell, respectively.The results demonstrated that the area of power balanced counter is only 2.167 x as much as the other. So we can conclued that the power balanced standard cell has higher practicailiby.
Keywords/Search Tags:power attack, cipher chip, auxiliary circuit, power balanced flip-flop, power balanced standard cell
PDF Full Text Request
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