Research On Testing Structure Automatically Building In IC Technology

In the past few decades, microelectronic technology get a rapid development, while a variety of electronic product applications has made modern IC system large and complexity, then more and more challenges are bring to the integrated circuit manufacturing techniques. Design for manufacturing on integrated circuits at this time was introduced to IC. As the requirements in the design for manufacturing as well as the IC system size and complexity, testing has been larger used in IC process, and its importance is also growing . Then the sub-micron and nano-Age is coming, test structures are becoming more complex, a wide range of uses are varied. IC manufacturers' const testing increases to more high, especially in the establishment of a large-scale chip of the test structure of time and labor costs.This article proposes a different approach with the traditional territory of the establishment of large-scale test structure methods - automatically build test structure. This approach uses parametric methods to build a hierarchical structure of a single type of test templates, and then used for large-scale instances of the template to complete the entire test chip, accomplished with a software in the whole process. When building a template structure, there are two important ways, one to set the properties of graphic elements to control the graphic elements of the size, shape, layer and location. Second, use constraints to control the relative positions of the different graphic elements, as a graphic element is selected as reference, location of other graphic elements are all determined. Then the template structure is assigned a serials of all the parameters to make a great quantity of instances. the whole process ia automatically operator by a software, then it can easily to quickly achieve the purpose of the territory of yield testing. This approach has three distinct advantages: 1. As the clearly hierarchy of the template structure, it's low probability to make mistakes; 2. Workload greatly reduced, saving time and cost; 3. When changes are required it is easier to change.This paper followed by a combination of engineering practice, proposes a new test poly stringer defect test structure and use the methods to build the test chips, they were manufactured together in a 0.11um copper process, then tested in wafer level. After testing and analysis the result, the fact comes that the new structure is better than the conventional test structure, and the factors which cause this defect was found, the foundry has derived new DFM rules to characterizing its process line's capability. The experiment greatly contributes to the further improvement on its product yield. The project also fully demonstrating the feasibility of this method and the high efficiency of this method.