SRAM-based Testchip Design For Yield Enhancement

In order to satisfy the requirement of data processing, high-performance SRAM increasingly occupy a majority of the chip area in SOC designs, Therefore, yield improvement of SRAM is essential to mass-production of advanced semiconductor products. In this paper a method of SRAM-based testchip design for yield enhancement and the test results of its tapeout are described. The main concern of this teschip is that how to design and use of SRAM-specif ic test structures for yield improvement. Compared with general test structures, SRAM-specific test structures are more SRAM-product-oriented to evaluate the device characters and real manufacturing yield. Test results show that SRAM-based testchip is able to capture defects which is impossible for general testchips, such as poly-diffusion contact short problem, further to correct design error for yield improvement.