Network On Chip Architecture Design And Performance Analysis

In the beginning of 21^st century, W.J.Dally brings forward the paradigm of on Chip Interconnection. To meet the demands of high bandwidth and low latency communication among modules on chip, Network on Chip technique grows up. Network on Chip is called NoC for short. The basic properties of NoC are, it presents a modular, component-based approach to hardware and software designs, using micro network to communicate among modules. NoC provides high bandwidth, low latency and scalability. NoC is similiar with conventional computer network, both of them need routers and topology. However, NoC has much difference with computer network. NoC is implemented on single chip, which has many limiting factors such as restricted area and power, and complex long link wire will result in larger cpu cycle time. Therefore, NoC design is doing trade-offs, among performance, hardware complexity and cost, providing good performance at the cost of little complexity and other cost.Because of the differences between NoC and conventional network, the NoC design is limit to many cost factors, such as area and power. The research object of this dissertation is that, based on the above limits, designing better network topologies, routers and their algorihms, so as to implement better NoC system, providing better system performance for CMP and other on chip systems.The content of this dissertation can be divided as NoC architecture design and performance analysis. The architecture design includes topology, scheduling algorithm and routing algorithm etc. performance analysis is evaluating and analyzing the performance of classic network architecture technologies, such as scheduling algorithm, routing algorithm, and flow control mechanisms. This dissertation is partitioned into three sections. The first section presents the international research status of recent years and the research platform in chapter 1, 2 and 3. The second section provides NoC architecture design in chapter 4 and 5. The last section gives performance analysis and conclusion in chapter 6 and 7.The research method of this dissertation is that: using the Popnet and Godson simulators, to make up the shortcomings of the classic network architecture, design and implement new topologies and routers, finally analyze and evaluate their performance. The contributions of this dissertation are shown as follow.The first innovative idea is that, this dissertation presents three new topologies Xmesh, Storus and Rgrid. Xmesh adds some links on the Mesh topology, reducing the hops among nodes, at the same time increasing the ideal throughput of the topology, Xmesh adapts to small-scale network. Storus rotates some links of Torus, the edges of Storus forms two Hamilton cycles, Storus adapts to multicast and broadcast traffic. Rgrid is a scalable topology, it doesn't add long link wire, it suits small and middle scale on chip network.The second innovative idea is three scheduling algorithms, which use three different items as scheduling standards. Compared to round-robin, these new scheduling algorithms can reduce the largest and average routing latencies, consequently improve the system performance.The third innovative idea is a routing algorithm called Ant_routing. Ant_routing is designed based on Ant Colony Algorithms, which select the path based on the amount of the information in the links. The amount of the information represents the amount of traffic load. This routing algorithm can alleviate the congestion induced by heavy traffic load.In conclusion, this dissertation optimizes NoC performance by topology, routing, scheduling algorithm design, provides more and better design options for NoC, gives some experiential conclusions by performance analysis.