Research On Topology And Routing Algorithm Of Photonic Interconnection Network-on-chip

Nowadays, with the rapid development of high-performance computers and high-performance microprocessors, interconnection network-on-chip becomes a hot research topic. Interconnection network-on-chip is used for the interconnection communication between a number of processor cores. Interconnection network-on-chip architecture determines the performance of the high-performance microprocessor. The traditional electrical interconnection network-on-chip architecture has some problems like low bandwidth, high latency, high power consumption and so on. While photonic interconnection network-on-chip architecture can effectively avoid high latency, high power consumption and other issues. Therefore, it is of importance to analysis on this topic.In this paper, to solve the problems mentioned above, we propose a novel photonic interconnection network-on-chip CLNOC, introduce its characteristic and extension method. Compared with Fat-Tree network-on-chip, CLNOC has lower devices cost, insertion loss and end-to-end delay. We also propose a hybrid opto electronic architecture to complete message switching.According to the characteristic of the CLNOC, we design a routing algorithm which can make full use of the cross-link. We use OMNeT++ and PhoenixSim to analyze CLNOC. Compared with the Mesh network, the performance of CLNOC is better.In this paper, we also design a photonic switching array, and extend its architecture to meet the demand of high-performance microprocessor. Compared with the Crossbar photonic switching array, our photonic switching array has lower devices cost and insertion loss. Finally, we propose a 3D CLNOC architecture.By analyzing and making full use of photonic interconnection network-on-chip architecture, we can design high-performance topology structure, routing algorithm, and switching method, improve the utilization of network bandwidth and link, reduce interconnection latency, and improve the reliability, scalability and performance of interconnection network-on-chip.